Field of the Invention
The present invention relates to Class AB amplifiers, and particularly but not exclusively to envelope tracking power supplies incorporating Class AB amplifiers.
Description of the Related Art
Envelope tracking applications may require an error amplifier with the ability to output a wide range of output currents at a high frequency. An example implementation of envelope tracking is an envelope tracking power supply with a switched supply to provide most of the wanted signal energy, and an error amplifier to remove unwanted switching artefacts which provides the remainder of the signal energy. Such an amplifier must have high efficiency, be linear, and must be able to handle high bandwidth signals.
Typically the error amplifiers of such implementations are Class AB amplifiers and are required to handle high peak-to-mean current swings. However, if correctly sized to handle large peak-to-mean current swings, a conventional Class amplifier typically requires a large quiescent current.
A typical prior art approach for a Class AB error amplifier in an envelope tracking power supply is to provide two transistors that each handle the positive and negative excursions of the waveform respectively. A typical Class AB amplifier has an input stage and an output stage. Typically, the input stage is run in Class A. As such, an existing Class AB arrangement typically consists of an input stage with a single output feeding into an output stage which contains a split at the input. This arrangement accounts for a high standing power dissipation which is typically observed in many high bandwidth amplifiers. The use of current amplification allows the maximum bandwidth to be extracted from the transistors.
An output stage of an exemplary Class AB amplifier of the prior art is illustrated in FIG. 1, and comprises a first stage 10 and a second stage 12. A single line feed to the input stage of the Class AB amplifier is represented by an input feed current source having current Iinput designated by reference numeral 3.
The first stage 10 has the single input Iinput and comprises a first pair of transistors M1 and M100 which handle input signals from the single input current Iinput on the positive excursion. The transistors M100 and M1 are connected in a current mirror arrangement, with the transistor M100 diode connected. A bias current Ibias+ denoted by reference numeral 5 is provided for the transistor M100 from a positive supply rail VDD, to keep the transistors M100 and M1 switched on. The input feed current Iinput is connected to the transistor M1.
The first stage 10 additionally comprises a second pair of transistors M2 and M200 which handle input signals from the single input current Iinput on the negative excursion. The transistors M200 and M2 are connected in a current mirror arrangement, with the transistor M200 diode connected. A bias current Ibias− denoted by reference numeral 7 is provided for the transistor M200 from a negative supply rail Vss, to keep the transistors M200 and M2 switched on. The input feed current Iinput is connected to the transistor M2.
A DC constant voltage Vref denoted by reference numeral 9 is applied to a common connection of the transistors M100 and M200 of the first stage 10. The DC constant voltage Vref determines the voltage at which the transistors M1 and M2 switch on. The DC constant voltage Vref source is connected between the negative supply rail Vss and the common connection of the transistor M100 and M200.
The transistors M1 and M2 of the first stage 10 split the input signal supplied by the input feed Iinput. The transistor M1 provides a positive part of the input signal Iinput+ on line 11, and the transistor M2 provides a negative part of the input signal Iinput− on line 13.
The first stage 10 thus has one input Iinput and two outputs Iinput+ and Iinput−.
The second stage 12 comprises a high-side (or positive) current mirror arrangement 14 provided by transistors M3 and M4. The high-side (or positive) current mirror arrangement 14 receives the positive part of the signal Iinput+. The high-side (or positive) current mirror arrangement 14 provides current from the upper supply VDD to an output current Iout, denoted as a positive output current Ioutput+.
The second stage 12 also comprises a low-side (or negative) current mirror arrangement 16 provided by transistors M5 and M6. The low-side (or negative) current mirror arrangement 16 receives the negative part of the input signal Iinput−. The low-side (or negative) current mirror arrangement 16 returns current to the lower supply Vss from the output current Iout, denoted as a negative output current Ioutput−.
The positive output current Ioutput+ and the negative output current Ioutput− are combined to form the output current Iout on line 15.
In order to prevent a loss of gain at the crossover point, both transistors M4 and M5 simultaneously conduct in the crossover region. By making both transistors conduct, it is possible to offset the loss in gain of the individual transistors M4 or M5 at low currents.
However, when used as part of the error amplifier in an envelope tracking arrangement (such as an envelope tracking power supply), the second stage 12 must handle a large range of currents, but unfortunately most of the distribution of currents required occurs around the centre of the output waveform exactly where the crossover region is located, and where the currents are relatively small. Thus the arrangement is sized to handle large currents, although most of the time the arrangement handles small currents.
If the transistors are sized correctly to output the maximum current required, in order to satisfy the Class AB criterion of maintaining the gain through the crossover region, a large quiescent bias current is required. The large quiescent bias current typically largely offsets the efficiency gain from using envelope tracking, especially at backed-off output powers. This large quiescent current is required to satisfy operation requirements for large currents, even though most of the operation is for smaller currents in the crossover region.
Another issue that arises relates to the Gm/C factor. The Gm/C factor determines the high frequency response of the output transistors M4 and M5. It is desirable for the Gm/C factor to be high, for improved linearity and low output impedance. However the Gm/C factor varies with current. This variance results in the transistors operating with low Gm/C factor at the points of operation where a high Gm/C factor is most required, i.e. at low currents in the crossover region. At high currents, the gm/C factor is highest, but since this area of operation (outside the crossover region) is accessed infrequently, there is no benefit obtained from the improved linearity and low output impedance at these currents.
The high Gm/C factor for high currents may further potentially give rise to a problem, because the loop gain of the feedback is pushed up bringing a risk of high frequency instability.
FIG. 2 shows an exemplary effect of gain on operating this type of Class AB output stage. The aim is to get the roll-off in Gm of the low-side output transistor (M5) to be compensated for by the rise in gain of the high side output transistor (M4). The standing current IQ is placed at the point where the gains overlap, and therefore each is 6 dB down. With a typical CMOS output stage the IQ can be as much as 20% of the full output current.
Reference numeral 200 denotes a plot of gain against current for the high-side (positive excursion) wide current range output stage. Reference numeral 202 denotes a plot of gain for the low-side (negative excursion) output stage. Reference numeral 204 denotes a plot of the combined gain. Reference numeral 206 denotes zero current on the x-axis of the plots, reference numeral 208 denotes the quiescent current on the x-axis of the plots, and reference numeral 210 denotes a maximum current on the x-axis of the plots.